Error Detection and Correction in 32-bit Sram Based Fpga Memory Using Decimal Matrix Code

The CMOS technology scales down to nano scale and memories are combined with an increasing number of electronic systems; the error rate in memory cells is rapidly increasing. Especially error occurs when memories operate in space satellites due to ionizing effects of atmospheric neutron, alpha-particle, and cosmic rays. SRAM Based FPGA’s are used mostly in Space satellites, which are sensitive to Radiation. Although single bit upset is a major concern about memory reliability, Multiple Cell Upsets have become a serious reliability concern. In order to make memory cells as fault-tolerant as possible, some error correction codes have been widely used to protect memories. Decimal Matrix Code (DMC) is proposed to detect and correct multiple bit errors that occur due to Radiation. The proposed DMC utilizes decimal algorithm to obtain the maximum error detection capability. Xilinx ISE 13.2 Software is used for the simulation outputs. Moreover, the Encoder-Reuse Technique is proposed to minimize the area overhead of extra circuits without disturbing the whole encoding and decoding processes. Encoder Reuse Technique uses DMC encoder itself to be part of the decoder. The Simulation output shows that the Decimal Matrix Code is more effective than existing Hamming and Matrix codes in terms of Error Correction Capability. The Power consumption is reduced in DMC. The Proposed DMC method has superior level of protection against Multiple Cell Upsets.